1st MLCAD Contest

IEEE/ACM MLCAD 2023 FPGA Macro-Placement Contest

Macro placement plays an integral role in routability and timing closure in both the ASIC and FPGA physical design flows. In particular, the discrete and columnated nature of the FPGA device layout presents unique placement constraints on placeable macros (e.g., BRAM’s, DSP’s, URAM’s, cascaded shapes, etc.). These constraints are challenging for classical optimization and combinatorial approaches, and often the generated floorplans result in netlist design placements with routing and timing closure issues. Inspired by recent deep reinforcement learning (RL) approaches (e.g. [1]), the goal of the competition is to spur academic research for developing ML or deep RL approaches to improve upon the current state-of-the-art macro placement tools.

Relevant Contest Dates

Apr 15, 2023	The Benchmark suite dataset will be provided and the call for participation published.
May 15, 2023	Registration deadline, details see below.
Jul 15, 2023	Each team must submit an alpha binary submission for test purposes, otherwise will be disqualified from the contest.
Aug 15, 2023	Teams must submit their final executable binaries by 11:59pm (pacific time).
Sep 13, 2023	Announcement of the contest results during MLCAD 2023.

Prizes

Prizes will be awarded to the top three teams. More details on this will be announced on the contest website soon. Prizes will be awarded to the top 5 teams at the 2023 MLCAD Workshop.

1^st Place: $2,500
2^nd Place: $1,500
3^rd Place: $1,000
4^th/5^th Places: $500

Important note on prizes
1. 40% of each Final Prize is awarded for performance in the contest according to the defined evaluation metric. The remaining 60% is awarded if the team publishes their winning software as open source under a permissive open-source license (BSD, MIT, Apache), within 30 days of being announced as a winner.
2. Applicable taxes may be assessed on and deducted from award payments, subject to U.S. government policies.

The Challenge

Benchmark Suite Dataset

The organizers will provide a public benchmark suite dataset (180 designs) using enhanced bookshelf format. There will also be an unpublished blind benchmark suite dataset totally 60 designs. You can download the public benchmark dataset from Kaggle. Please refer to the dataset’s documentation for a full description of the file format. Each design in the benchmark suite contains the following files:

File	Description
design.nodes	Specifies placeable instances in the netlist (in Bookshelf format).
design.nets	Specifies the set of nets in the netlist (in Bookshelf format).
design.lib	Specifies the cell library for placeable objects.
design.pl	Specifies the site locations of the macros including cascaded macro shape instances, I/O, and fixed objects. This supplied file only contains locations of fixed instances (IBUF/OBUF/BUFGCE etc.). Your task is to supply the locations of the placeable macro instances. Valid locations for macro (and cascaded shape) instances are prescribed in the design.scl file.
sample.pl	Specifies a macro placement sample reference solution.
design.scl	Extended from the original bookshelf format to represent XCVU3P device layout and permissible site locations for all placeable object types (please refer to the figure at the top).
design.cascade_shape	Specifies the types of placeable cascaded macro shapes.
design.cascade_shape_instances	Specifies the netlist instances of cascaded macro shapes.
design.regions	Specifies the box region constraints imposed on placeable objects
design.dcp	This file contains the synthesized netlist checkpoint that is required as an input by the Vivado executable.
place_route.tcl	A TCL script to place and route a netlist using the Vivado flow leveraging the input macro placement solution.

FPGA Device Description

The FPGA architecture used in the contest will be based on an UltraScale+ XCVU3P monolithic device. Please refer to the UltraScale Architecture and Product Data Sheet: Overview (DS890) documentation for more details. The organizers reserve the right to modify the contents of the benchmark designs and format.

Evaluation Metrics

The macro placement solution produced by participating placers will be evaluated using the Vivado physical design compiler. Contestant teams will be provided with a Vivado license and a place-and-route flow that reads an input macro placement in the extended bookshelf format, check macro placement legality, and perform standard cell placement and routing. The place-and-route flow will be non-timing driven for this contest. The macro placement solution will be evaluated based on the following criteria:

1. Legality of the macro placement
2. Total routed wirelength and routing congestion metrics (within a time-out limit of 6 hours)
3. Macro placement runtime
4. Total placement and routing runtime of the Vivado place and route flow

The scores will be tallied based on performance on both the publicly released benchmark dataset (180 designs) and an unpublished blind benchmark dataset (60 designs). Further details will be provided on the contest’s official website.

Macro-Placement Solution Guidelines

We encourage teams to develop a ML-based approach, but teams are free to use any approach (e.g., classical optimization, combinatorial, ML, RL, etc.) for their macro-placement solution.

Contact

For registration and contest related inquiries, please email: [email protected].

Acknowledgements

The organizers wish to thank Zhiang Wang, Yuji Kukimoto, Sreevidya Maguluri, Ravishankar Menon, Nima Karimpour-Darav, Mehrdad Eslami, Chaithanya Dudha, Lin Chai, Kai Zhu, Vishal Suthar, Parisa Rahimian, Kristin Perry, Mark O Brian, James Chik, Derrick Woods, and Cathal McCabe for their helpful remarks, advice, and assistance.